Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible failures. Therefore, improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults based CMPs. There exists several address application cores while placing spare onto topologies. However, these limited Mesh topology NoCs. few approaches have realized solutions an FPGA, but study architectural aspects of limited. This paper presents flexible placement core Torus topology-based design considering validating it FPGA. first phase, mathematical formulation Integer Linear Programming (ILP) meta-heuristic Particle Swarm Optimization (PSO) been proposed core. second we implemented router addressing scheme, routing algorithm, run-time fault injection model, using Experiments done taking different multimedia synthetic benchmarks. both static dynamic simulation environments followed hardware implementation. environment, experimentations carried out scaling network size network. The results obtained from our approach outperform methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), Genetic Algorithm (GA) literature. For experiments size, methodology shows average improvement 18.83%, 4.55%, 12.12% cost over FSCM, SA, GA, respectively. network, 34.27%, 26.26%, 30.41% simulations, 5.67%, 0.44%, 3.69%, implementation, 5.38%, 7.45%, 27.10% terms runtime superiority presented